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| 1/30 L4969 september 2000 this is preliminary information on a new product now in development. details are subject to change without notice. n operating supply voltage 6v to 28v, transient up to 40v n low quiescent current consumption, less than 100 m ain sleep mode n two very low drop voltage regulators 5v/100ma and 5v/200ma n separate voltage regulator for can-transceiver supply with low power sleep mode n reset logic n serial interface n can transceiver (low speed, double wire) with fault tolerance n voltage sense comparator description the L4969 is an integrated circuit containing 3 inde- pendent voltage regulators and a standard fault tol- erant low speed can line interface in multipower bcd3s process. it integrates all main local functions for automotive body electronic applications connected to a can bus. so20 powerso20 ordering numbers: L4969md (so20) L4969 (powerso20) product preview system voltage regulator with fault tolerant low speed can-transceiver figure 1. block diagram vreg 1 vreg 2 vreg 3 fault tolerant low speed can-transceiver 24 bit spi control and status memory identifier filter watchdog and adjustable rc-oscillator vs v1 v2 v3 canh canl rth rtl tx rx sclk sin sout wake nint nreset
L4969 2/30 figure 2. pin connection table 1. pin functions table 2. thermal data note: 1. typicalvaluesolderedonapcboardwith8cm 2 copper ground plane (35 m mthick). pin no. (pso20) pin no. (so20) pin name function 1, 10, 11, 20 5,6, 15, 16 gnd power ground 2 7 v1 microcontroller supply voltage 3 8 v2 peripheral supply voltage 4 9 v3 internal can supply 5 10 vs power supply 6 11 canh canh line driver output 7 12 rtl canl termination source 8 13 canl canl line driver output 9 14 rth canh termination source 12 17 rxd act. low can receive dominant data output 13 18 txd act. low can transmit dominant data input 14 19 sout serial data output 15 20 sin serial data input 16 1 sclk serial clock 17 2 nres act. low reset output 18 3 nint act. low interrupt request 19 4 wake dual edge triggerable wakeup input symbol parameter value unit r thj-a thermal resistance junction-ambient 40 1) k/w r thj-c thermal resistance junction-case 3 k/w nint wake gnd gnd v1 v2 v3 vs canh rtl canl rth rx gnd gnd tx sout sin sclk nres so20 gnd v1 v2 v3 vs canh rtl canl rth gnd gnd wake nint nres sclk sin sout txd rxd gnd pso20 3/30 L4969 table 3. absolute maximum ratings notes: 1. the circuit is esd protected according to mil-std-883c. 2. current forced means voltage unlimited but current limited to the specified value. voltage forced means voltage limited to the specified values while the current is not limited. table 4. electrical characteristcs v s = 14v, t j =-40 cto150 c unless otherwise specified. symbol parameter value unit v vsdc dc operating supply voltage -0.3 ... +28 v v vstr transient operating supply voltage (t < 400ms) -0.3 ... +40 v i vout1... i vout3 output currents internally limited t stg storage temperature -65 ... +150 c t j operating junction temperature -40 ... +150 c v out1 externally forced output voltage out1 -0.3 ... +6.3 v v out2 externally forced output voltage out2 -0.3 ... vs+0.3 v v out3 externally forced output voltage out3 -0.3 ... +6.3 v v inli input voltage logic inputs: sin, sout, rxd, sclk -0.3 ... +7 v v inliw input voltage wake -0.3 ... vs+0.3 v v canh voltage canh line -10 ... +27 v v canht voltage canh line t < 0.1ms -40 ... +40 v v canl voltage canl line -10 ... +27 v v canlt voltage canl line t < 0.1ms -40 ... +40 v item symbol parameter test conditions values unit min. typ. max. 1 supply current 1.1 i ssl all regulators off, (can standby) 100 m a 1.1.1 i sslwk v1 off, v2 off, v3 on (can rx only) 4ma 1.2 i ssb v1 only (can standby) 200 m a 1.3 i s all regulators on, (can active, tx high) i out1 = -100ma i out2 = -10ma no can load. 150 ma L4969 4/30 2 voltage regulator 1 2.1 v 01 v1 output voltage 6v < v s <28v -400 m a< -i o <-100ma 4.9 5 5.1 v 2.2 v 01 t j < 125c -50 m a<-i o <-400 m a 4.7 5 5.3 v 2.3 v dp1 dropout voltage 1 v s =4.8v 2.4 i out1 = -10ma 0.1 0.2 v i out1 = -100ma 0.2 0.4 v 2.5 v ol01 load regulation 1 -1ma <-i o <-100ma 40 mv 2.6 i lim1 current limit 1 0.8v < v o1 < 4.5v 105 200 400 ma 2.7 v oli1 line regulation 1 6v < v s <28v i o1 = -1ma 30 mv 2.8 t ovt1 overtemp flag 1 6v < v s < 28v 140 c 2.9 t otkl1 thermal shutdown 1 6v < v s < 28v 200 c 2.10 v res min v1 reset threshold voltage rtcr = 0 4.5 v rtcr = 1 4.0 v 3 voltage regulator 2 and 3 3.1 v o output voltage 6v < v s <28v -1ma <-i o <-200ma 4.8 5 5.2 v 3.2 v dp dropout voltage i out = 200ma v s =4.8v 0.7 v 3.3 v olo load regulation -1ma < -i o < -200ma 50 mv 3.4 i lim current limit 0.8v < v o < 4.5v 210 400 800 mv 3.5 v oli line regulation 6v < v s <28v i out = -5ma 75 mv 3.6 t ovt overtemp flag 6v < v s < 28v 140 c 3.7 t otkl thermal shutdown 6v < v s < 28v 170 c 4 reset and watchdog 4.1 t rdnom reset pulse duration 0.5 1 1.5 ms 4.2 t wdstart reset pulse pause (startup watchdog) 38 47.5 57 ms item symbol parameter test conditions values unit min. typ. max. table 4. electrical characteristcs (continued) 5/30 L4969 4.2.1 t wdsws watchdog window start (software window watchdog) swdc = 8 2 2.5 3 ms swdc = 9 4 5 6 ms swdc = 10 8 10 12 ms swdc = 11 20 25 30 ms 4.2.2 t wdswe watchdog window end (software window watchdog) swdc = 8 4 5 6 ms swdc = 9 8 10 12 ms swdc = 10 16 20 24 ms swdc = 11 40 50 60 ms 4.3 t wd1c system watchdog 1 wd1c = 8 60 80 100 ms wd1c = 9 120 160 200 ms wd1c = 10 250 320 400 ms wd1c = 11 500 640 780 ms wd1c = 12 640 800 980 ms 4.4 t wd2c system watchdog 2 wd2c = 8 0.75 1 1.25 s wd2c = 9 1.5 2 2.5 s wd2c = 10 3 4 5 s wd2c = 11 6 8 10 s wd2c = 12 30 45 60 min 4.5 v resl reset output low voltage r resv1 = 10k v1 > 1.5v 0.4 v 5 can line interface 5.1 v droph canh voltage drop (dominant state) i canh = 40ma 1.4 v 5.2 v dropl canl voltage drop (dominant state) i canl = -40ma 1.4 v 5.3 t d propagation delay (rec to dom state) c load = 3.3n 1 m s 5.4 s rd bus output slew rate (r -> d) 10% ... 90% c load = 3.3n 5v/ m s 5.5 r rth ,r rtl termination resistance 0.5 16 k w 5.6 v ccfs force standby mode (fail safe) v s 2.75 4.5 v 5.7 vh rxd high level output voltage on rxd v3 - 0.9 v3 v item symbol parameter test conditions values unit min. typ. max. table 4. electrical characteristcs (continued) L4969 6/30 5.8 vl rxd low level output voltage on rxd 0 0.9 v 5.9 vd_r differential receiver dom to rec threshold v canh -v canl no bus failures (common mode range 5v) -3.25 -2.65 v 5.10 vr_d differential receiver rez to dom threshold v canh -v canl no bus failures (common mode range 5v) -3.25 -2.65 v 5.11 vd_r f differential receiver dom to rec threshold v canh -v canl bus failures (common mode range 5v) 0.4 0.7 1 v 5.12 v canhr canh recessive output voltage txd = v1 r rth <4k 0.2 v 5.13 v canhd canh dominant output voltage txd = 0 i canh =40ma v3 - 1.4v v 5.14 v canlr canl recessive output voltage txd = v1 r rtl <4k v3 - 0.2v v 5.15 v canld canl dominant output voltage txd = 0 i canl = -40ma 1.4 v 5.16 i canh canh dominant output current txd = 0 v canh =0v -70 100 -130 ma 5.17 i canl canl dominant output current txd = 0 v canl =14v 70 100 130 ma 5.18 i lcanh canh sleep mode leakage current sleep mode. v canh =0v 0 m a 5.19 i lcanl canl sleep mode leakage current sleep mode. v canl =0v v s =12v 0 m a 5.20 v wakeh canh wakeup voltage sleep/ standby mode 1.2 1.9 2.7 v 5.21 v wakel canl wakeup voltage sleep/ standby mode 2.4 3.1 3.8 v 5.22 v canhs canh single ended receiver threshold normal mode. -5v 9/30 L4969 1.0 functional description 1.1 general features the u435 is a monolithic integrated circuit which provides all main functions for an automotive body can network. it features two independent regulated voltage supplies v1 and v2, an interrupt and reset logic with internal clock generator, serial interface and a low speed can-bus transceiver which is supplied by a separate third voltage regulator (v3). the device guarantees a clearly defined behavior in case of failure, to avoid permanent can bus errors. the device operates in three different modes: a) sleep mode: v1 is off v2 is off v3 is off can-transceiver: active with reduced performance watchdog active 9.7 t eiv canl to gnd short circuit detection time operating mode (eiv) 0.4 0.9 1.8 ms sleep/ standby mode (eiv) 0.4 0.9 1.8 ms 9.8 t eivr canl to gnd short circuit recovery time operating mode (eiv) 10 30 50 m s sleep/ standby mode (eiv) 0.4 0.9 1.8 m s 9.9 t evi canl to vs short circuit detection time operating mode (evi) 0.4 0.9 1.8 m s 9.10 t evir canl to vs short circuit recovery time operating mode (evi) 200 500 750 m s 9.11 t evii canl to canh short circuit detection time operating mode (evii) 0.4 0.9 1.8 ms 9.12 t eviir canl to canh short circuit recovery time operating mode (evii) 10 30 50 m s 9.13 t eviii canh to vdd short circuit detection time operating mode (eviii) 0.9 1.8 3.6 ms sleep/ standby mode (eviii) 0.9 1.8 3.6 ms 9.14 t eviiir canh to vdd short circuit recovery time operating mode (eviii) 0.4 0.9 1.8 ms sleep/ standby mode (eviii) 0.4 0.9 1.8 m s 9.15 t failtx tx permanent dominant detection time (fail safe) operating mode (ex) 0.4 0.9 1.8 ms 9.16 t failtxr tx permanent dominant recovery time (fail safe) operating mode (ex) 1 4 8 m s item symbol parameter test conditions values unit min. typ. max. table 4. electrical characteristcs (continued) L4969 10/30 the total current consumption is < 100 m a. b) standby mode: v1 is on ( m c in stop mode) v2 is off v3 is off can-transceiver: active with reduced performance the total current consumption is < 200 m a. c) operating mode: v1 is on v2 is on v3 is on v1 output voltage the v1 regulator uses a dmos transistor as an output stage. with this structure very low dropout voltage at currents up to 100ma is obtained. the dropout operation of the standby regulator is maintained down to 4v input supply voltage. the output voltage is regulated up to the transient input supply voltage of 40v. with this feature no functional interruption due to overvoltage pulses is generated. the output 1 regulator is switched off in sleep mode. through metal option the output 1 voltage can be set to 3.3v. v2 output voltage the v2 regulator uses the same output structure as the output 1 regulator except to being short circuit proof to vs, and to be rated for the output current of 200ma. the v2 output can be switched on and off through a ded- icated enable bit in the control register. in addition a tracking option can be enabled to allow v2 follow v1 with constant offset. this feature allows consistent a/d conversion inside the m c (supplied by v1) when the convert- ed signals are referenced to v2. v3 output voltage the third voltage regulator of the device generates the supply voltage for the internal logic and the can-trans- ceiver. in operating mode it is capable of supplying up to 200ma in order to guarantee the required short circuit current for the can_h driver. the sleep and operating modes are switched through a dedicated enable bit. internal supply voltage a low power sleep mode regulator supplies the internal logic in sleep mode. 1.2 can transceiver C supports double wire unshielded busses C baud rate up to 125kbaud C short circuit protection (battery, ground, wires shorted) C single wire operation possible (automatic switching to single wire upon bus failures) C bus not loaded in case of unpowered transceiver the can transceiver stage is able to transfer serial data on two independent communication wires either def- erentially (normal operation) or in case of a single wire fault on the remaining line. the physical bitcoding is done using dominant (transmitter active) and overwritable recessive states. too long dominant phases are detected internally and further transmission is automatically disabled (malfunction of protocol unit does not affect com- munication on the bus, "fail-safe" - mechanism). for low current consumption during bus inactivity a sleep mode is available. the operating mode can be entered from the sleep mode either by local wake up ( m c) or upon de- tection of a dominant bit on the can-bus (external wake up). ten different errors on the physical buslines can be distinguished: 11/30 L4969 1.3 detectable physical busline failures not all of the 10 different errors lead to a breakdown of the whole communication. so the errors can be categorized into 'negligible', 'problematic' and 'severe': negligible errors transmitter error i and ii (canh or canl interrupted but still tied to termination) error iv and viii (canh or canl permanently dominant by short circuit) in all cases above data can still be transmitted in differential mode. receiver error i and ii (canh or canl interrupted but still tied to termination) error v and ix (canh or canl permanently recessive by short circuit) in all cases above data can still be received in differential mode. problematic errors transmitter error iii and vi (canh or canl show overvoltage condition by short circuit) data is transmitted using the remaining dataline (single wire) receiver error iii and vi (canh or canl show overvoltage condition by short circuit) data is received using the remaining dataline (single wire) n type of errors conditions errors caused by damage of the datalines or isolation i canh wire interrupted (tied to ground or termination) edgecount difference > 3 ii canl wire interrupted (floating or tied termination) edgecount difference > 3 iii canh short circuit to v bat (overvoltage condition) v(canh) > 7.2v after 32us iv canl short circuit to gnd (permanently dominant) v(canl) < 3.1v & v(canh)-v(canl) < -3.25v after 1.3ms v canh short circuit to gnd (permanently recessive) edgecount difference > 3 vi canl short circuit to v bat (overvoltage condition) v(canl) > 7.2v after 32us vii canl shorted to canh v(canh) - v(canl) < -3.25v after 1.3ms errors caused by misbehavior of transceiver stage viii canh short circuit to vdd (permanently dominant) v(canh) > 1.8v & v(canh) - v(canl) < -3.25v after 1.3ms ix canl short circuit to vdd (permanently recessive) edgecount difference > 3 errors caused by defective protocol unit x canh, canl driven dominant for more than 1.3ms L4969 12/30 severe errors transmitter error v and ix (canh or canl permanently recessive by short circuit) data is transmitted on the remaining dataline after short circuit detection error vii (canh is shorted to canl) data is transmitted on canh or canl after overcurrent was detected error x (attempt to transmit more than 10 successive dominant bits (at lowest bitrate specified) transmission is terminated (fail safe) receiver error vii (canh is shorted to canl) data is received on canh or canl after detection of permanent dominant state error iv and viii (canh or canl permanently dominant by short circuit) data is received on canh or canl after short circuit was detected error x (reception of a sequence of dominant bits, violating the protocol rules) data is received normally, error is detected by protocol-unit the error conditions is signaled issuing an error flag inside a dedicated register which is readable by the m c through the serial interface. the information of the error type (i through x) is also stored into this register. 1.4 oscillator a low power oscillator provides an internal clock. in sleep mode (watc hdog active) the output frequency is 250khz, if the watchdog function is not requested, the internal oscillator is switched off. in standby and operating mode the oscillator is running at 1mhz, and can be calibrated in a range from -16% to +16% using the m c-xtal as a reference. 1.5 watchdog a triple function programmable watchdog is integrated to perform the following tasks: C wakeup watchdog: when in sleep or standby mode the watchdog can generate a wakeup condition after a programma- ble period of time ranging from 80ms up to 45 minutes C startup watchdog: upon v1 power-up or m c failure during spi supervision (see sw-watchdog) a reset pulse is gener- ated periodically every 50ms for 2.5ms until activity of the m c is detected (spi sequence) or no ac- knowledge is received within 7 cycles (350ms). in this condition the device is forced into sleep mode until a wakeup is detected and a startup cycle is reinitialized. C window watchdog: after passing the startup sequence, this watchdog request an acknowledge by the m cviathespi within a programmable timing frame, ranging from 2.5 ... 5ms up to 20 ... 40ms. upon a missing or misplaced acknowledge the startup watchdog is initialized. 1.6 identifier filter a 12-bit can-id-filter is implemented allowing wakeup via specific can-messages thus aiding the implemen- tation of low power partial communication networks like standby diagnostics without the need to power-up the whole network. to guarantee the detection of the programmed identifiers, the local rc-osc illator can be calibrated to allow the programmable bittime logic to extract the incoming stream with a maximum of tolerance over temperature de- viation. 13/30 L4969 1.7 power-on reset upon power-on (vs > 3.5v), the internal reset forces the device into a predefined power-on state: v1 on v2 off v3 off can-standby mode id-filter disabled startup watchdog active with vs below 5v the regulator v1 will follow vs with minimum drop. the m c retrieves a reset if v1 is dropping below a programmable voltage level of either 4.5v (default) or 4.0v. the programmed state of the u435 remains unchanged. 1.8 ground shift detection in case of single wire communication via canh the signal to noise ratio is low. detecting the local ground shift can be used as an additional indicator on the current signal quality. the information of the integrated ground shift detector will be refreshed upon every fa lling edge on tx and can be read from the can transceiver status register (ctsr). it will be set, if v(canh) < -1v, reset if v(canh > -1v) at the falling edge of tx. 1.9 thermal protection the device features three independent thermal warning circuits which monitor the temperature of the v1 output, the v2 output and the can_h and can_l drivers together with voltage regulator v3. each circuit sets a sepa- rate overtemperature flag in a register which is read and writable by the serial interface. the overtemperature flags cause an interrupt to the m c. the m c is able to switch v1, v2 and can drivers on and off through dedicated enable registers. to enhance system security following strategy is chosen for thermal warning and shutdown: C 3 independent warning flags are set at 140c for v1, v2 and v3/can-transceiver C at 170c v2 and v3 switched off C at 200c v1 is switched off C v2 and v3 can be switched on again through the m c C v1 can be switched on again at wake-up (watchdog wake-up, can wake-up, external wake-up) note, that if no wakeup source is set for v1 a 1sec watchdog timeout will be established to enable a proper retry cycle. 1.10 serial interface (spi) a standard serial peripheral interface (spi) is implemented to allow access to the internal registers of the u435. a total of 12 registers with different datalengths can be directly read from or written to, providing the requested address at the beginning of a dataframe. upon every access to this interface, the content of the register currently accessed is shifted out via sout. all operations are performed on the rising edge of sclk. if a frame is not completed, the interface is automatically reset after 1.5ms of sclk idle time (auto timeout detection). due to limited pin count on this device the chip select has to be programmed explicitly (see tristate sout) and will return to the normal output mode after a fixed period of 1.5ms after the last foreign spi interaction. the dataframe format used described below: L4969 14/30 general dataframe format: data is sampled on the rising edge of the clock and sout will change upon sclk falling. sout will show a copy of sin for the address/command field for initial data path checks. independent of the command state, sout will show the content of the register addressed. sin contains either data to be written or arbitrary data for all other operations. the transaction will be terminated with four bit of data followed by a 4-bit wide crc (cyclic redundancy check) as a result of either sin related data or calculated automatically on data returned via sout. here the m c has to provide the correct sequence in order to get the write command activated inside. a crc-failure is signalled via nint. for returned data the crc can also be used to verify a successful transfer. address/command field the address/command field starts with a 2-bit start sequence consisting of 01. any other sequence will lead to a protocol error signalled via the nint. the addressfield is specifying the register to be accessed. the spi command flags allow in addition to the normal read/write operation to either clear a register after read (operating only on ifr) or to disable sout to allow communication between m c and other peripherals using the same spi. the sout function is automatically reestablished after 1.5ms following the last transaction and will be signalled via nint. sclk sout adr/cmd datafield 1 (r) datafield 2/crc (r) 0 7 15 23 sin 0 adr/cmd 7 datafield 1 (w/r) 15 datafield 2/crc (w/r) 23 99at0015 0 1 adr3 adr2 adr1 adr0 c1 c0 0 7 frame start sequence always has to be transmitted as 01 addressfield specifying the control/status word to be accessed spi command: 00: read register 01: clear register 1) 10: tristate sout 2) 11: write register 1) clear register can only be performed with the interrupt flag register ifr at adr6 2) tristate sout has to performed on address 15 99at0016 15/30 L4969 datafield #1 datafield #1 contains either the lower 8 bits of a 12-bit frame or the complete byte of an 8-bit transfer. note, that sout is always showing the content of the register currently accessed and not a copy of sin as dur- ing the address/ command field. datafield #2/crc datafield #2 contains either the upper four bits of a 12-bit frame or zeros in case of an 8-bit transfer. this field is followed by a four bit crc sequence that is calculated based upon the polynom 0x11h (17 decimal). this sequence is simply the remainder of a polynomial division performed on the data previously transferred. if the crc appended to the sin sequence fails, any writing will be disabled and an error is signalled via nint. another remainder is calculated on the sout stream and appended accordingly to allow the application software to val- idate the correctness of incoming data. to aid evaluation, the crc checking can be turned off by writing arbi- trary data with a valid crc to address 15. crc-checking will be reenabled upon another operation of this kind (toggled information). d7 d6 d5 d4 d3 d2 d1 d0 sin: data to write sout: data currently in selected register lower 8 bit of 12 bit data 99at0017 d11 d10 d9 d8 crc3 crc2 crc1 crc0 sin: data to write sout: data currently in selected register upper 4 bit of 12 bit data (zero if 8 bit data) crc check sequence to be appended to tranferred data note that upon crc check failure no write operation will be performed sin: crc of sin sequence sout: crc of sout sequence 99at0018 L4969 16/30 1.11 memory map the memory space is divided up into 16 different registers each being directly accessible using the spi. each register contains specific information of a functional group. in general al reserved bitpositions (res) have to be written with 0. undefined bits are read as 0 and cannot be overwritten. in addition there is one register (ctsr) being read only, thus any write attempt will leave the register content unchanged. certain interlock mechanism exist to prevent unwanted overwriting of important functions i.e. voltage regulators or oscillator adjustments. these mec hanisms are described with the functions of these registers. table 5. u435 memory map adr group msb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 vrcr undefined register memory euv3 euv2 rtc0 trc res env3 env2 disar 1ctcr act txen res res res res res res 2 gptr res res res res tm1 tm0 tmux ten 3 rcadj cg1 cg0 pgen sign adj3 adj2 adj1 adj0 4wdc wden swen swt1 swt0 wdt3 wdt2 wdt1 wdt0 5gien iset ires euv eovt eew ecw eww eifw 6ifr espi iset ires uv23 uvvs ovt3 ovt2 ovt1 wke wkc wkw wkif 7 ctsr res res res gsh ex eviii evii evi eiv eiii eii ei 8id01 c11 c10 c01 c00 b11 b10 b01 b00 a11 a10 a01 a00 9id23 f11 f10 f01 f00 e11 e10 e01 e00 d11 d10 d01 d00 10 btl ps23 ps22 ps21 ps20 ps13 ps12 ps11 ps10 td3 td2 td1 td0 11 nav undefined register memory 12 nav 13 nav 14 test t11 t10 t09 t08 t07 t06 t05 t04 t03 t02 t01 t00 15 sys undefined register memory crc tri wndf stf otf ucf wake npor 17/30 L4969 2.0 control and status registers the functionality of the device can be observed and controlled through a set of registers which are read and writable by the serial interface. adr 0: vrcr voltage regulator control register trc disable all regulators (go to sleep) enable regulator #3 . this function will automatically be activated upon enabling of the can lineinterface enable regulator #2. enable regulator #2 tracking option res to have v2 following v1 with constant offset rtc0 set reset threshold value to 4.0v default value is 0 (4.5v) euv2 euv3 env3 env2 disar reserved bits (res) have to be written as 0. default value is 0 (disabled) default value is 0 (disabled) this bit will be automatically reset upon overtemperature from canif or regulator #3 default value is 0 (disabled) this bit will be automatically reset upon overtemperature at regulator #2. d7 d0 disar v1 v3 disar &env3 nstb & otkl3 trc v2 disar &env2 note, that at least one wakeup source is required to be set to enable access. this bit will be automatically set upon overtemperatue at regulator #1 and reset upon wakeup or power on. if no wakeupsource was specified, the 1 sec watchdog timer is activated. default vaue is 0 enable undervoltage detection on regulator #2 and #3 ref L4969 18/30 adr 1: ctcr can-transceiver control register three basic operating modes are available using different logic combinations on act and txen. each of these modes in conjunction with other inputs has its unique combination of parameters inside the specification: table 6. operating modes of the can lineinterface input signals output signals act txen tx canh canl v3 mode rtl rth canh canl rx 0 x x rth rtl on standby v bat gnd off off 1 1 0 1/0 rth rtl on rxonly v dd gnd off off tx 1 0 1 rtl on rxonly v dd gnd off off 1 0 1 rth on rxonly v dd gnd off off 1 1 1 rth rtl on normal v dd gnd on on 1 1 1 0 rth rtl on normal v dd gnd vdd gnd 0 1 1 1 rtl on normal v dd gnd on on 1 1 1 rth on normal v dd gnd on on 11 0 *1 rth rtl on error x v dd gnd off off 1 1x1 vdd *1 rtl on error vii, viii v dd isrc off on canl 1x1 vs *1 rtl on error eiii, vii, viii v dd isrc off on canl 1 x 1 gnd x 3 on error ei_v v dd gnd on on 1x1 x3v dd on error eii_ix v dd gnd on on 1x1rth vs *1 on error evi isrc gnd on off canh 1x1rth gnd *1 on error evii, eiv isrc gnd on off canh 1x1 canl *1 canh *1 on error evii isrc gnd on off canh res txen act res res res reserved bits (res) have to be written as 0. can-transceiver application control 0x : standby / sleep 10 : receive only mode a (readback tx, if not ex) 11 : normal operation d7 d0 note, that txen is automatically reset upon occurence of ex (tx permanent dominant) and has to be reprogrammed after problem correction to enter normal mode. res res *1) shorted to ... 19/30 L4969 adr 2: gptr global parameter and test register adr 3: rcadj rc-oscillator adjust register during normal operation the m c can set cg1 and cg0 to 01 to force a 200hz rectangular waveform on nint with 50% duty cycle. note, that all other pending interrupts have to be cleared before. after the xtal driven timer of the m c calculated the relative cycle time and the corresponding deviation, cg1 and cg0 have to be set to 10 to disable the adjustment cycle on nint. from the deviation calculated by the m c, the correction factor of the rc-oscillator -16% to + 16% can be reprogrammed with cg1 and cg0 set to 00 or 11. (11 can be used to indicate that calibration has already been performed). note, that overwriting this register is only valid, if the cycle measurement was started and terminated properly. this can be tested by evaluating pgen either prior to or during correction (read back via sout). res res res res d7 d0 tm1 tm0 tmux ten this register is to be used for testpurpose only, all bits have to remain zero cg1 cg0 pgen adj4 adj3 adj2 adj1 adj0 d7 d0 00: no request (adjustment disabled) 01: 2.5ms low cycle on nint (repetitive) 10: finish cycle measurement 11: no request (adjustment disabled) test cycle request a low pulse on nint for a fixed period of time can be requested for xtal synchronization program enable (read only) bit will be set after test cycle completion, and reset after register write 0: +16% 1: 0% 0: 0% 1: -8% 0: 0% 1: -4% 0: 0% 1: -2% 0: 0% 1: -1% rc oscillator frequency adjust default value 10000 note, that programming is only enabled with pgen set 99at0022 L4969 20/30 adr4: wdc watchdog control register the startup watchdog is not programmable and will always generate a 2.5ms low cycle on nreset followed by a 47.5ms high cycle until an acknowledgment will occur. if no acknowldege is received after the 7th cycle, the device will automatically be forced into sleep mode. acknowledgment and reset of startup and window watchdog is automatically performed by overwriting (or rewriting) this register. watchdog configuration: after power-on-reset of vs and v1 or wakeup from sleep or nreset being forced low externally, the startup watchdog is active, supervising the proper startup of the v1 supplied uc. upon missing spi write operation to the wdc register after 7 reset cycles (2.5ms active, 47.5ms high) the sleep mode is entered. leaving the forced sleep mode will be automatically performed upon wakeup via can, an edge on wake or upon device powerup. after successful startup, the window watchdog supervision is activated, meaning, that the uc has to send an acknowledge within a predefined, programmable window. upon failure, a reset is generated and the startup watchdog is reactivated. if the timer function is requested, the window watchdog is deactivated until expiry of the wakeup time. swt0 wdt3 swt1 res wden wdt2 wdt1 wdt0 d7 d0 wakeup watchdog timing configuration 0000 : 80ms 0001 : 160ms 0010 : 320ms 0011 : 640ms 0100 : 800ms 1000 : 1sec 1001 : 2sec 1010 : 4sec 1011 : 8sec 1100 : 45min software window watchdog timing configuration 00 : 2.5 - 5ms 01 : 5 - 10ms 10 : 10 - 20ms 11 : 20 - 40ms enable wakeup watchdog, window watchdog will be automatically deactivated until wakeup watchdog expires reserved bits (res) have to be written as 0. startup window wakeup forced sleep wd wd ack ack missing ack timer wr & wden timeout missing ack (after 350ms) extwake can-wake por prog sleep wakeup nreset forced low externally 21/30 L4969 1: startup after powerup, the u435 is expecting the uc to send an acknowledgement within a predefined segmented tim- ing frame of 7 x 50ms. a missing acknowledgement until after the 350ms will force the device into sleep mode until either external or can wakeup or por cause a restart of the sequence above. 2: window watchdog after successful acknowledgement of the startup sequence, the window watchdog is automatically activated and controlling pr oper uc activity by supervising an incoming acknowledge to ly within a predefined program- mable window. upon every acknowledge the watchdog is restarting the window. 3: wakeup watchdog if the timer is activated during normal mode by setting wden in wdc, an acknowledge-free sequence is started for a predefied programmable time. window watchdog activity is resumed after expiry of the timer. to be able to detect the timeout, the corresponding interrupt enable must be set in gien. this mode can also be used to allow a bootstrap loader mode with longer execution times than the maximum specified window. correct startup of this loader is safely detected upon missing response following the timeout. v1 nreset nreset nreset startup acknowledgement via spi within 50ms startup acknowledgement via spi within 100ms no startup acknowledgement via spi within 350ms (device will enter sleep mode) 2.5ms early (late) acknowlede supervision 2,5 .. 20ms 5 .. 40ms 50% acknowledge is restarting window early (late) acknowlede supervision window wd window wd timer (80ms .. 45min) nint ack window & start timer timeout and resume window wd interrupt active upon timeout (via gien) L4969 22/30 adr5: gien global interrupt enable register adr6: ifr interrupt flag register except espi all bits in this register are maskable in gien. any masked bit will force nint low until the register content is reset (either explicitly or by spi clear register). eovt eew euv ires iset ecw eww eifw d7 d0 enable identifier based wakeup / interrupt enable wakeup,/ interrupt via watchdog enable can dominant state / error enable wakeup / interrupt viaedgeonwake wakeup / interrupt enable interrupt upon can error recovery enable interrupt upon can error detection enable interrupt upon overtemp. warning enable interrupt upon vs / vreg undervoltage d11 d0 espi iset ires uv23 wkif wkw wkc wke ovt3 ovt2 ovt1 uvvs vs < 7.2v detected overtemperature warning level reached ovt1 : t(v1) > 140degc ovt2 : t(v2) > 140degc ovt3 : t(v3) > 140degc signal edge on wake detected wakeup condition via can detected watchdog timeout detected identifier passed can id-filter reserved bit (res) has to be written as 0. crc- / format error or sclk- timeout detected by spi (non maskable) can linefailure detected (iset) removed (ires) v2 or v3 undervoltage 23/30 L4969 adr7: ctsr can transceiver status register note, that this register is read only and only provides the unlatched information on current buserrors. identifier of can frame can be divided up into 6 segments numbered from a to f. for each segment a filter register is implemented, enabling different pass functions on every two bit wide block. segments a through c (id01) are located at adr 8 with msb c11 segments d through f (id23) are located at adr 9 with msb f11 note, that clearing a complete segment disables the whole filter. d11 d0 res res res gsh ei_v eii_ix eiii eiv eviii evii evi ex reserved bits (res) are always read as 0 canh < -1v at falling edge tx tx permanent dominant detected canh permanent dominant detected (txd = 0, t > 1.3ms) (canh > 1.8v, t > 1.3ms) short circuit canh to canl detected (canh - canl > -3.25v, t > 1.3ms) canl short circuit to vs detected (canl > 7.2v, t > 32us) canl permanent dominant detected (canl < 3.1v, t>1.3ms) canh short circuit to vs detected (canh > 7.2v, t > 32us) single wire communication detected (edge count difference > 3) ei_v : canh off eii_ix : canl off 10 01 00 10 01 01 00 01 01 10 00 10 01 11 01 01 01 01 sega segb segc examples: identifiers to pass: sega: a10, a00 0011 0010 id01: 0011 0010 0101 0101 segb: b01 segc: c01, c00 segf: f10, f01 segd: d10, d01 sege: e11, e01, e00 1011 id01: 0110 1011 0110 0011 0110 id bits to be set segf sege segd valid sequence for each segment L4969 24/30 adr 10: btl identifier filter bittimelogic control register the total bitlength equals the sum of pseg1 + pseg2 in units of m s. the location of the sampling point is determined by the length of pseg1. at the start of frame (initial recessive to dominant edge) the bitlength counter is reset. upon every signal edge the counter will be lengthened or shortened according to location of the transition within the programmed boundaries of pseg1 or pseg2. if the edge lies within pseg1 additional cycles are inserted in order to shift the sampling point to a safe location after the settling of the input signal. if the signal transition is located within pseg2, this segment will be shortened accordingly with the goal of the next edge to lie at the beginning of pseg1. the amount of cycles one segment is lengthened or shortened is determined by the type of edge (rec -> dom or dom -> rec) and the programming of td: the resynchronization jump width will be either set to 1 (dom -> rec edge) or to 1 + td (rec -> dom edge). note, that the length of one timequanta depends on the offset of the on chip rc-osc illator and therefore on the accuracy of calibration (see register rcadj (adr 3) for details on frequency correction) ps23 ps22 ps21 ps2 ps13 ps12 ps11 ps10 d11 d0 dominant to rezessive bitlength difference control t dom = t rez + td[ m s] td3 td2 td1 td0 phasesegment 1 length configuration t pseg1 = 1 m s x (1 + ps1) phasesegment 2 length configuration t pseg2 = 1 m s x (1 + ps2) t = 1 m s bittime synchronization mechanism pseg1 pseg2 sample point 99at0030 25/30 L4969 adr 15: sys system status register the lower 6 bit of this register can be used to analyze the reason of startup (after nreset low). this information is valid until the first watchdog-acknowldge, and will then be reinitialized to 000001. stf otf wndf tri crc ucf wake npor d7 d0 crc-checking enabled warm start after failure of window watchdog tristate sout activated (test only) warm start after < 7 missing ack during startup warm start after v1 overtemp failure warm start after 7 missing ack during startup warm start after leaving prog. sleep mode cold start after low vs L4969 26/30 3.0 interrupt management all interrupt flags (in ifr) except espi can be masked in the global interrupt enable register (gien). an interrupt will be signalled by nint going low until either the corresponding mask or the flag itself will be reset by the application software. an autoreset function is available for ifr, allowing to remove all interrupt flags after reading their state (see spi). eovt eew euv ires iset ecw eww eifw d7 d0 d11 d0 espi iset ires uv23 wkif wkw wkc wke ovt3 ovt2 ovt1 uvvs gien ifr nint 27/30 L4969 4.0 remarks for application general circuit connection diagram thermal supervision standby supply & adjustable rc-oscillator programmable timer wakeup & interrupt detection wake v3 sout sin sclk spi gnd can transceiver groundshift detection id-filter rth v2 v1 rx tx canh canl rtl vs nint nres peripheral supply m c other peripherals 33 m f 99at0032 L4969 28/30 11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data 29/30 L4969 jedec mo-166 powerso20 e a2 a e a1 pso20mec detail a t d 1 11 20 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 10? (max.) s t10 0.394 (1) "d and f" do not include mold flash or protrusions. - mold flash or protrusions shall not exceed 0.15 mm (0.006"). - critical dimensions: "e", "g" and "a3" outline and mechanical data 8? (max.) 10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 30/30 L4969 |
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